This invention relates to a method of treating an integrated circuit.
A charge-coupled device (CCD) may be made by processing a silicon wafer of p conductivity using conventional MOS technology to form a plurality of buried channels of n conductivity beneath the front surface of the wafer (the surface through which the wafer is processed). Each channel is made up of a linear array of like elementary zones. A clocking electrode structure overlies the front surface of the wafer, and by application of selected potentials to the clocking electrode structure, charge present in a given elementary zone of a channel may be advanced through the linear array of elementary zones, in the manner of a shift register, and extracted from the channel. Charge may be generated in the channels photoelectrically. Thus, if electromagnetic radiation enters the wafer it may cause generation of conduction electrons and these conduction electrons may become confined in one of the elementary channel zones.
A known type of CCD has three distinct functional components formed in different regions of a single silicon die. The buried channels are formed in a channel region. In operation, the channel region is clocked between voltages of approximately 7-15 volts relative to the substrate, which is typically held at 0 volts. Charge that is propagated to the output ends of the buried channels is applied to an output amplifier which is formed in an amplifier region of the CCD. The output amplifier normally includes at least one field effect transistor. In the known type of CCD the substrate bias in the amplifier region is the same as that in the channel region.
The field effect transistor of the output amplifier is generally operated with a large potential difference between the source and substrate and between the drain and substrate. This is required because the gate of the output transistor is connected to an output diode which is required to operate at a voltage of the order of 15 V. The large drain to substrate voltage causes the transistor to operate in an undesirable fashion. First, the large reverse bias on the drain causes light emission to occur from the junction. This light may propagate through the die of the known type of CCD and result in generation of conduction electrons in the buried channels, thus adding noise to the signals received by the output amplifier from the buried channels. Second, the large drain to substrate bias forces the transistor, which is normally of the buried channel type, to operate in the surface channel mode. That is, the conduction channel, which normally would reside away from the silicon/silicon dioxide interface, is forced to the surface. This contributes additional noise to the output signal.
It is known to use a level shifting amplifier to couple useful signal information from a first circuit node at a first potential to a second circuit node at a second potential. However, it would not be practicable to use a level shifting amplifier to couple the output diode of a CCD to the gate of the output field effect transistor, because it would be the first amplifier in a chain of amplifiers and would inevitably introduce substantial noise into the output signal provided by the amplifier chain. The clock electrodes of the CCD are connected to clock drivers, which may be formed in a clock driver region of the wafer. The clock drivers are used to change the potentials of the clock electrodes at a high frequency, and therefore rapidly changing electric fields are generated by the clock drivers. In the known type of CCD, these fields are coupled through the die to the channel region, and influence the quantity of charge confined in the buried channels.
A CCD may be used to generate a two-dimensionally sampled electrical signal representative of the distribution of light intensity over the channel region of the CCD. In such an imaging CCD, it is desirable that the thickness of the die be not much greater than the depth of the interface between the channels and the substrate. This may be achieved by securing the wafer at its front surface to a reinforcing member, and thinning the wafer from its back surface.